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Pa-Risc 2.0 Architecture
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Ubicado en: San Rafael, California, Estados Unidos
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Entrega prevista entre el mar. 19 ago. y el vie. 22 ago. a 94104
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N.º de artículo de eBay:156607902258
Última actualización el 11 ago 2025 18:04:54 H.EspVer todas las actualizacionesVer todas las actualizaciones
Características del artículo
- Estado
- ISBN
- 9780131827349
Acerca de este producto
Product Identifiers
Publisher
Prentice Hall PTR
ISBN-10
0131827340
ISBN-13
9780131827349
eBay Product ID (ePID)
46119
Product Key Features
Number of Pages
496 Pages
Language
English
Publication Name
Pa-Risc 2. 0 Architecture
Subject
Systems Architecture / General, Microprocessors, Hardware / Personal Computers / General
Publication Year
1995
Type
Textbook
Subject Area
Computers
Format
Trade Paperback
Dimensions
Item Height
0.7 in
Item Weight
27.2 Oz
Item Length
7 in
Item Width
9.3 in
Additional Product Features
Intended Audience
Scholarly & Professional
LCCN
95-049176
Dewey Edition
20
Illustrated
Yes
Dewey Decimal
004.1
Table Of Content
1. Overview. Traditional RISC Characteristics of PA-RISC. PA-RISC-The Genius is in the Details. A Critical Calculus: Instruction Pathlength. Multimedia Support: The Precision Process Illustrated. Integrated CPU. Extensibility and Longevity. System Organization. 2. Processing Resources. Non-Privileged Software-Accessible Registers. Privileged Software-Accessible Registers. Unused Registers and Bits. Data Types. Byte Ordering (Big Endian/Little Endian). 3. Addressing and Access Control. Physical and Absolute Addressing. Virtual Addressing. Pointers and Address Specification. Address Resolution and the TLB. Access Control. 4. Page Table Structure. Caches. Control Flow. Branching. Nullification. Instruction Execution. Instruction Pipelining. 5. Interruptions. Interrupt Classes. Interruption Handling. Instruction Recoverability. Masking and Nesting of Interruptions. Interruption Priorities. Return from Interruption. Interruption Descriptions. 6. Instruction Set Overview. Computation Instructions. Multimedia Instructions. Memory Reference Instructions. Long Immediate Instructions. Branch Instructions. System Control Instructions. Assist Instructions. Conditions and Control Flow. Additional Notes on the Instruction Set. 7. Instruction Descriptions. 8. Floating-point Coprocessor. The IEEE Standard. The Instruction Set. Coprocessor Registers. Data Registers. Data Formats. Floating-Point Status Register. Floating-Point Instruction Set. 9. Floating-Point Instruction Set. 10. Floating-Point Exceptions. Exception Registers. Interruptions and Exceptions. Saving and Restoring State. 11. Performance Monitor Coprocessor. Performance Monitor Instructions. Performance Monitor Interruptions. Monitor Units. Glossary. Appendix B. Instruction Formats. Appendix C. Operation Codes. Appendix D. Conditions. Appendix E. Instruction Notation Control Structures. Appendix F. TLB and Cache Control. Appendix G. Memory Ordering Model. Appendix H. Address Formation Details. Appendix I. Programming Notes. Appendix J. PA-RISC 2 Instruction Completers & Pseudo-Ops.
Synopsis
For system designers and analysts, system software programmers, application developers, and technical managers. Hewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA-RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor., Synthesizing the literature from related fields including macroeconomics, technology transfer, and innovation, the author's rigorous methodology shows that Total Factor Productivity is positively related to GDP and is mediated by research and development., Hewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA- RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor. For system designers and analysts, system software programmers, application developers, and technical managers.
LC Classification Number
QA76.8.H48K36 1996
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